erlendgausen.net

By popular request, configuration files for a simple 4-1 multiplexer realised in PAL and a template file for writing JEDEC compliant PALASM configuration files.

I wrote these files during my college studies, but despite PALs now being quite outdated by cheap, flexible and reprogrammable microcontrollers there still appears to be interest for exploring programmable logic circuits as they are the foundation for todays powerful FPGAs.

Function logic operators:

* = AND
+ = OR
/ = NOT

Multiplexer function file:

TITLE 4-1 MULTIPLEXER
PATTERN 4-1mux.pds
REVISION 1.0
AUTHOR Erlend Gausen
DATE 22.03.99
CHIP PAL16R8
PIN 1 CLK COMBINATORIAL ;INPUT
PIN 2 D0 COMBINATORIAL ;INPUT
PIN 3 D1 COMBINATORIAL ;INPUT
PIN 4 D2 COMBINATORIAL ;INPUT
PIN 5 D3 COMBINATORIAL ;INPUT
PIN 6 A0 COMBINATORIAL ;INPUT
PIN 7 A1 COMBINATORIAL ;INPUT
PIN 10 GND ;INPUT
PIN 11 OE COMBINATORIAL ;INPUT
PIN 12 UT REGISTERED ;OUTPUT
PIN 20 VCC ;INPUT

EQUATIONS
D0=/A*/B
D1=/A*B
D2=A*/B
D3=A*B

SIMULATION
TRACE_ON D0 D1 D2 D3 A0 A1 UT
SETF /OE
SETF /A /B
CLOCKF CLK
CHECK D0 D1 D2 D3 A0 A1 UT
SETF /A B
CLOCKF CLK
CHECK D0 D1 D2 D3 A0 A1 UT
SETF A /B
CLOCKF CLK
CHECK D0 D1 D2 D3 A0 A1 UT
SETF A B
CLOCKF CLK
CHECK D0 D1 D2 D3 A0 A1 UT
TRACE_OFF

Template file:

TITLE -
PATTERN - ;(name of source file)
REVISION v1.0
AUTHOR Erlend Gausen
COMPANY I speak for myself
DATE 1999.04.11CHIP ;(Which PAL circuit to be used)
; -*- Pin declarations
; syntax: PIN 1 CLK COMBINATORIAL;INPUT

PIN 1
PIN 2
PIN 3
PIN 4
PIN 5
PIN 6
PIN 7
PIN 8
PIN 9
PIN 10
PIN 11
PIN 12
PIN 13
PIN 14
PIN 15
PIN 16
PIN 17
PIN 18
PIN 19
PIN 20
; -*- Optional section
; syntax: STRING STATE_1 ‘X * /Y * Z * etc
; STRING
; -*- Function equations for combinational logic
; -*- SIMULATION